Mixed Signal IP Platforms for Cellular Applications
Chipidea is the only provider in the market to offer a full suite of Analog/Mixed-Signal Embedded IP for Cellular applications,
enabling SoC innovation through analog subsystems and IP. This will allow you to access to advanced analog solutions, adding value to Your products with mature IP and with very quick development
cycles, down to 65nm today.
The functions Chipidea supports include the Analog Baseband (ABB) and 3GDigRF
to interface with the Cellular RF chip-set, Audio Codecs, Power Management and USB,
targeting the process nodes of 130nm, 90nm, 80nm and 65nm.
Block Diagram of a cellular phone
Chipidea ABB's interface the digital baseband processor to the RF chip-set.
These self-contained cores include all the converters and filters required for reception, transmission and radio control.
Main features are:
Highly programmable to support different RF chip-sets, allowing multimode radios (eg. EGPRS and WCDMA);
Upgradeable to support the new standards of 3G LTE and WiMax;
Very compact 10-bit DACs for Radio control and 10-bit ADCs with multiplexed inputs for system monitoring;
Rx Path based on a reconfigurable Sigma-Delta modulator, providing optimized current consumption both for EGPRS and WCDMA mode,
saving chip area by re-using the same IP core;
Tx Path includes digital interpolation filters, I&Q DACs and voltage or current output modes;
Customized to specific requirements, supporting wide range of systems (GSM/EGPRS, CDMA, TD-SCDMA, WCDMA/UMTS, etc)
See CI7640tm
for very compact embedded core solutions.
See also CI7625tg
for high performance companion die solutions. For the Rx path only, use CI3383tn.
Block Diagram of Cellular ABB
Click in the thumbnail to view the full size image.
Chipidea IP DigRF line is a complete chip-to-chip interface between the RF chip-set and the baseband ICs for
cellular systems. It is compliant with 3G DigRF V3.07 specifications. It includes a master interface (digital baseband side) and a slave
interface (RF IC side), with a controller and a physical layer (PHY) for a complete, fully integrated link (block diagram bellow).
See CI14112.
The Controller IP offers full programmability through the AMBA port, and other standard ports are available upon request and is
available as a soft macro for foundry-independent integration.
The PHY is a mixed-signal macroblock and is foundry dependent. The IP features simple, three-pin clocked serial
protocol layers, a configurable PLL and configurable line-driver output for low power consumption.
Block Diagram of DigRF
Chipidea Power Management functions specially suited for Cellular applications (see diagram below), are possible in
130nm, 90nm and 65nm chips with very small chip area, allowing direct connection to the battery.
Block Diagram for Power Management functions.
Click in the thumbnail to view the full size image.
Special IPs are:
Highly Programmable Buck and Buck-Boost DCDC converters, highly Efficient, Capable of connecting directly to
Lithium Batteries 2.7V-4.3V; Programmable Output Voltage Range: 0.8V-3.4V in steps of 100mV; Modular for output load currents from
100mA up to 600mA; Efficiency above 95%; Quiescent current of 100uA (CI2512tm,
CI2514vg);
Universal Linear Regulators with external capacitor: Programmable Output Voltage Range: 0.8V-3.4V in steps of 100mV; LDO modular for output load
currents from 25mA up to 300mA. Used to supply both analog and digital power islands and external chip-sets (CI2423##);
Capless Linear Regulators Programmable Output Voltage Range: 0.8V-3.3V in steps of 100mV. Used to supply the
internal chip power domains (CI2337tg);
Complete Power Management Units, can also be provided combining the above IP plus Power-On reset, RTC oscillators, Temperature
Sensors, Battery Chargers and many other auxiliary functions.
Chipidea Audio Codecs are specially suited for mobile cellular applications.
CI7825tl
main features are: drive line ability; headphone and loudspeakers (no need for external AC coupling capacitors); amplify from line or
microphone levels both differentially and single ended; independent volume controls and mixer schemes, etc., using 2.8V supplies; Low
Power consumption (12mW in playback at 48kHz sampling), small area (2.7sqmm analog for a complete codec) and great performance
(96dB Dynamic Range in the full audio band). See block diagram below.
Block Diagram of Audio Codec
Click in the thumbnail to view the full size image.
Chipidea USB is the wired interface of choice for mobile cellular applications, by combining power supply and data
communication is the same physical interface. ChipIdea offers a complete solution comprising a family of USB Link Controllers and USB
Physical layers that are silicon proven and USB-IF certified.
Check here our USB information.
CI12343tn
is the first industry’s USB High Speed PHY with Certification in TSMC65nm, with the lowest area and power consumption - less than
80mW - and innovative features of charger detection and parameterizable waveform shape (amplitude, rise/fall times, slope).
Check here our PHY information.
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