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NEWSLETTER 01 - 2008   
   
 

Dear IP User,

Happy New Year 2008!
In this issue, we provide the SoC (System-On-Chip) community with the latest analog/mixed-signal news from Chipidea, including:

 
 
 

When designing your next Wireless USB System, please consider the broad offering of silicon-proven IP and expertise that Chipidea offers.

The diagram below shows an example of a W-USB dongle, with Chipidea IP blocks in blue.
Wireless USB Dongle general block diagram
Wireless USB Dongle general block diagram


 
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The latest data converters for emerging UWB systems include the new (CI3419im) Dual ADC and the (CI8529im) Dual DAC. These converters can be used in UWB communications including Wireless USB, Bluetooth over UWB, Wireless FireWire (W-1394) and other wireless personal networks. They can also be used in end applications such as W-USB dongles, PDAs, PMPs, smart phones, notebooks, printers, video systems, cameras, and more. Both converters have excellent performance and can be licensed separately or integrated in a complete UWB RF transceiver.

New USB PHY in 45nm Key Benefits:
  • Fast time-to-production and time-to-revenue (TTM/TTR)
  • Reduced risk with simple SoC integration: internal reference generation and no external components
  • Extremely low power with a very compact design
  • High speed: up to 1GHz data conversion rate
  • 5/6-bit IQADC, 6-bit IQDAC of resolution
Cutting edge experience of more than 10 years in data conversion!
  • Reduced risk solutions: Chipidea's market leadership, with 25% market share in data conversion (Gartner Dataquest Inc. 2006) is the result of 10 years of cutting edge expertise.
  • Silicon proven: Many years (>5) of several I&Q matched ADC/DAC designs across various processes, silicon proven, for integration in Wireless Data Communication SoCs.
  • IEEE recognition: Chipidea developed 90nm high-speed data converter (1GHz ADC) 3 years ago. Our (CI3412) IP design is a state-of-the-art (first-time right) silicon proven solution recognized by IEEE.
All about ADC, DAC and AFE here.

 
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The new USB High-Speed Inter-chip PHY (CI12410) is the first IP core available on the market for USB HS Inter-chip communication, and an unprecedented solution for chip-to-chip connectivity. It offers a unique opportunity for software reuse as chip-to-chip communication becomes encapsulated and abstracted into USB software, assuring reduced time-to-market and reduced risk (see block diagrams below):

Key Benefits:
  • Dramatic cost reduction of including USB connectivity in a chip: the IP core is a replacement of a USB 2.0 mixed-signal macrocell, and can be 0.013 sqmm small in 65nm. This digital core is 5K gates small.
  • Reduced power consumption: low-power interface, since the clock is active only during active transmission/reception on the bus.
  • Compatibility with Chipidea USB Controller: the (CI12410) can be combined with the usual mixed-signal USB 2.0 PHYs for cable connectivity.
(CI12410) USB HS Inter-Chip PHY block diagram
(CI12410) USB HS Inter-Chip PHY block diagram

(CI12410) USB HS Inter-Chip PHY in an application
(CI12410) USB HS Inter-Chip PHY in an application


 
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Consolidating our leadership in providing the USB PHY in the most advanced technology nodes and in the broadest PHY offering in the market, Chipidea presents the new (CI12323tp) USB High-Speed OTG PHY in TSMC 45nm LP in 1.8V and 2.5V.
  • Reduced power consumption, next to its compact, silicon-saving design, makes the IP core especially well-suited for leading-edge mobile applications.
  • Outstanding/superior "Analog Programmability" allows fine-tuning of the analog parameters of your system, for excellent performance results in silicon.
  • Further range of applications is enabled by Link Power Management and Charger Detection functionality.
If you are looking for even more advanced nodes, we are already working on them! Contact us now at sales@mips.com.

 
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The new (CI2621tn) compact versatile 10 mA low-ripple, 2.5V-3.3V Charge-Pump IP, is designed to supply a wide range of cores in multiple applications including USB PHYs, audio codecs and wireless analog-front-ends.
Available in TSMC 65nm, this is the latest offering from a broad catalog of integrate-able power management IP here.

The IP core is a low ripple charge-pump with fast response and guaranteed stability with any load. Reliability is guaranteed by limiting the voltage seen by the charge-pump with the help of two external Schottky diodes. It uses digital control for excellent robustness.

Key Features:
  • 2.25 - 2.94 V input supply voltage
  • 3.3 V regulated output voltage
  • <20 mV output voltage ripple
  • 10 mA output current capacity
  • 2.0 MHz switching frequency
  • No inductors
  • 200µs soft start time
  • 50µA no load power consumption
  • below 1µA power down current
  • compact 0.2mm2 core area
(CI2621tn) Charge Pump Block diagram
(CI2621tn) Charge Pump Block diagram




 
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Chipidea's LVDS SerDes IP cores in 90nm and 65nm are available in silicon now! Our labs have performed extensive test and characterization of the LVDS test chips in 65nm and 90nm, showing excellent results in terms of compliance and performance. The figure below shows the LVDS line driver output at 1Gbit/s. These great results were also confirmed by customers who have included Chipidea's LVDS SerDes IP in their chips, currently in mass-production.
LVDS eye diagram
LVDS eye diagram


Test reports are available upon request. For more information on these and other LVDS configurations, contact us at sales@mips.com.

 
 
 

Chipidea expands its PLL portfolio with a family of high-performance PLLs, featuring much-reduced jitter for demanding applications. With jitter down to 5ps under specific conditions, these PLLs are ideally suited for jitter-sensitive applications, while maintaining programmability for multipurpose applications.

The latest additions to the "PLL High-Performance" portfolio are:
  • (CI19244tn): 500MHz Programmable Low Jitter General Purpose PLL TSMC 65nm LP
  • (CI19276tn): 1GHz Programmable Low Jitter General Purpose PLL TSMC 65nm LP
Find our PLL Portfolio here. Other configurations are available on request.

 
 
 

2007-12-10: Chipidea Introduces Industry's First Class D Audio Driver IP

2007-12-04: Chipidea Achieves Certification for USB High-Speed PHY IP on Chartered's 90nm and 65nm Customer-ready Technologies

2007-10-23: Chipidea and PLM Unveil New Chip Design Allowing Billions of People to Enjoy HD Content on CRT TV

For more information, please go to www.chipidea.mips.com or contact sales@mips.com.

 
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