Dear IP User,
In this issue we will provide the SoC (System-On-Chip) Community with our latest Analog /Mixed-Signal news:
With many years of expertise and working with market leaders, we help you select the most suitable IP for your system.
When designing your next notebook chip, please consider the broad range of Silicon IP and expertise that Chipidea has to offer (Chipidea Silicon IP in orange - diagram below).
Notebook Chip general block diagram
This new IP with less than 0.35mm2 is configurable as Single ADC (CI3423tn) for Analog Video and as Dual ADC (CI3636tn) for use in the receive channel of Wireless Broadband communication systems such as WiFi, Mobile TV (DVB-H, ISDB, DMB,) and mobile WiMAX/Wibro.
Besides the power saving modes, the dynamic power scaling ensures minimum power consumption for portable applications.
The ADC has excellent performance, gain and phase matching, supports a wide common mode input range and has pure internal voltage references.
For the same applications Chipidea has other compact and low Power ADC designs ready (CI3534) (CI3537), various complete and configurable Analog Front Ends (AFE) also for MIMO WiFi, (m) WiMAX/Wibro (CI7642tm) (CI7644tn) and complete Video AFEs.
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The 24-bit 90dB Dynamic Range 8 to 192kHz Sampling Rate Stereo Audio Codec IP (CI7824sm) is now available in Fujitsu 90nm. This is an optimized cost-performance audio codec, that enables high-fidelity audio quality with multiple analog interface capabilities, such as microphone, line-in/out, headphone and loudspeaker, compact analog area (2.95mm2) and low power operation (12mW @ Playback). Extended Audio functions such as Automatic Volume Control, phantom ground output, etc. are also included to offer enhanced Audio experience.
24 bit 90dB Dynamic Range 8 to 192kHz Sampling Rate Stereo Audio Codec block diagram
APPLICATIONS: MP3 Players/Recorders, PDAs, Mobile Phones and Smart phones.
Already available in TSMC 0.13um and 90nm (pre-silicon) and CSM 0.13um this IP will also be available soon in CSM 90nm and 65nm and in other tier-one Foundries.
The new IP core (CI10412tm) is a complete RF transceiver for WLAN, high data rate, and short-range communications, including the RF Front-end and the baseband converters, providing a digital interface to the digital PHY.
The core is optimized for embedded integration. Only the PA, RF switch and a small number of passive components are needed to form a complete RF solution. The baseband filtering and converters are programmable to support the different modes. Supports MiMo configurations by sharing the LO among several instantiations of the basic core.
In 90 nm CMOS technology, top metal in UTM, requiring no MiM capacitor, covers all world bands 2.412-2.484GHz & 4.915-5.795GHz and supports the standards 802.11 b/g/a/h/j/n.
Also featuring: Low-IF with digital de-rotation architecture, 64-QAM compliant; 1.2 V Single Supply; Low power consumption (220 mW w/ converters; 180 mW w/o converters); small core size (below 12 mm2 w/ converters; below 9 mm2 w/o converters).
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Chipidea introduces the new (CI2512tm) Step-Down DC-DC Converter in TSMC 90nm G and LP process flavours.
The DC-DC switcher converts an input supply voltage with a wide voltage range of Vin=1.7V-3.6V to an output voltage programmable in fine steps within the range of Vout=0.8V-1.4V.
The IP has the ability to maintain high efficiency (above 90%) over a large load range using PWM/VFM alternative controls switching at a frequency up to 2.2MHz.
It is optimized to achieve optimum efficiency up to a maximum output current of 600mA, with only 0.72mm2 including internal references, internal regulators, internal clock generator and system power-on-reset. The low quiescent current of 100uA is ideally suited for portable systems operating from a battery requiring long standby time.
The soft-start prevents large inrush currents at start-up, while internal current limitation mechanisms protect the circuit against short circuits on the output.
Block Diagram of CI2512
APPLICATIONS: Any SoC requiring voltage regulation with high efficiency, such as: MP3 Players/Recorders, PDAs, Mobile Phones, Smart phones and many other portable applications.
Also available in TSMC 0.13um and SMIC 0.13um. This IP will also be available soon in TSMC 65nm and in other tier-one Foundries.
The new Chipidea architecture is the latest from the industry's most prolific provider of USB IP solutions and achieves a low power consumption of around 70mW. The usage of IO Device of 1.8V is an industry first and extends Chipidea's USB catalog, from IO Devices of 3.3V and 2.5V, offering the widest range of options for USB connectivity integration strategies.
Fully compliant with the USB 2.0 specification, Chipidea's 1.8V USB PHY guarantees D+ and D- protection to withstand transient short-circuit voltage without damage. The core also features analog programmability for fine tuning, allowing designers to achieve the best performance of their integrated systems. The IP is available as a standalone PHY or matched with a USB controller.
Chipidea presents the LVDS Serializer & Deserializer IP in TSMC 65nm G+ technology.
Operating at speeds up to 1.05 Gbps, the LVDS IP is compatible with different Display applications, integrating currently High-Definition TV (HDTV) solutions.
The LVDS SerDes IP family has also been developed in 0.13um and 90nm processes, being available in a multiplicity of technical specifications to match the needs of every IP design.
Example of a 5-channel Serializer & Deserializer LVDS Block Diagram
- (Video DACs) - recent 10/12-bit Video DACs for portable applications and STB
- (CI12392tm) Dual-Port USB PHY in TSMC 90nm GOD. Designed on a modular architecture, it may be easily expanded up to 8 Ports. Some modularity advantages are the small area and power saving, when compared to a situation of several single-port PHYs on the same die. Dual-Port and Triple-Port versions have been successfully taped-out.
- (CI12343cn) USB 2.0 High-Speed OTG PHY in Chartered 65nm LP.
- (CI12343in) USB 2.0 High-Speed OTG PHY in IBM 65nm LP.
- USB 2.5v Family expansion:
New USB 2.0 OTG PHY, in TSMC 90nm LP and G technology flavours, expanding Chipidea's 2.5v architecture portfolio. These High-Speed 2.5v USB Physical Interfaces are currently available in 130nm, 90nm and 65nm, in major foundry processes.
- Introducing 55nm.
Chipidea will tape out soon a USB 2.0 OTG PHY in TSMC 55nm G+ 1.8v. This step towards miniaturization is aligned with the roadmap of ever-reduced tech nodes and reduced voltage. More information to be disclosed soon.
Find more details about our low risk silicon IP solutions at our website www.chipidea.com or contact us at sales@mips.com.
Best Regards
The Chipidea Team - Your Silicon IP Partner
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