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Chipidea Analog: Expanding the Digital Revolution
February 2007

Dear IP User,

If your application is in the Cellular field, you will find at Chipidea a wide portfolio of solutions that match your technical requirements at 180nm, 130nm, 90nm and 65 nm.

We support a large range of functions including Analog Baseband (ABB), 3GDigRF to interface with a separate Cellular RF chip, Power Management, Audio Codecs, and USB.

Block Diagram of a Cellular Phone
Block Diagram of a Cellular Phone

Chipidea Analog Baseband (AFE's)

The ABBs are  complete interface units located between the digital baseband processors and the RF sections. These self-contained cores include all the converters and filters required for reception, transmission, as well as monitoring and control functions.

Main features are:
  • Highly programmable interfaces supporting different RF chipsets, and multimode radios (eg. EGPRS and WCDMA);
  • Upgradeable capabilities to support 3G-LTE and WiMax
  • Compact 10-bit DACs for RF control and 10-bit ADCs with multiplexed inputs for system monitoring;
  • Rx Path based on reconfigurable Sigma-Delta modulator, providing optimized current consumption for EGPRS and WCDMA modes, saving chip area by re-using the same IP
  • Tx Path includes digital interpolation filters, I&Q DACs and voltage or current output modes;
  • Extensive support for multiple communication standards including GSM/EGPRS, CDMA, TD-SCDMA,WCDMA/UMTS, etc.
  • See CI7640tm for an example of a very compact embedded core solutions; CI7625tg for a high performance companion die solution; CI3383tn for a Rx path only core.
ABB Block Diagram
ABB Block Diagram

Chipidea IP DigRF solutions

Chipidea's DigrRF core is a complete chip-to-chip interface between the RF chip-set and the baseband ICs for cellular systems. Compliant with 3G DigRF V3.07 specifications, it includes a master interface (digital baseband side) and a slave interface (RF IC side), with a Controller and a Physical layer (PHY) for a complete, fully integrated link (diagram below). See CI14112.

DigRF Block Diagram
DigRF block diagram

Chipidea Power Management

Our Power Management solutions include a very compact set of functions specially suited for Cellular applications (see diagram below) including a direct interface to several kind of batteries.

Power Management function Block Diagram
Power Management function Block Diagram

Several cores including:
  • Highly Programmable Buck and Buck-Boost DCDC Converters, connecting directly to Lithium Batteries 2.7V-4.3V; Programmable Output Voltage: 0.8V-3.4V of 100mV steps; Modular for output load currents 100mA-600mA; Efficiency above 95%; 100uA quiescent current (CI2512tm, CI2514vg);
  • Universal Linear Regulators with external capacitor: Programmable Output Voltage Range: 0.8V-3.4V in steps of 100mV; LDO modular for output load currents 25mA-300mA, supplying analog and digital power islands and external chip-sets (CI2423##);
  • Capless Linear Regulators Programmable Output Voltage Range: 0.8V-3.3V of 100mV steps, supplying internal chip power domains (CI2337tg);
  • Complete Power Management Units combining above IP plus Power-On Reset, RTC oscillators, Temperature Sensors, Battery Chargers and other auxiliary functions.

Chipidea Audio Codecs

These Audio Codecs are specially suited for mobile cellular applications (CI7825tl) featuring:
  • Drive line ability;
  • Headphone and loudspeakers;
  • Amplify from line or microphone levels both differentially and single ended;
  • Independent volume controls and mixer schemes, using 2.8V supplies;
  • Low Power consumption (12mW in playback at 48kHz sampling);
  • Small area (2.7sqmm analog for a complete codec);
  • Great performance (96dB Dynamic Range in the full audio band).

Click in the thumbnail for larger view.

Chipidea USB

USB is the wired interface of choice for mobile cellular applications, by combining power supply and data communication in the same physical interface.
Chipidea offers a complete solution comprising a family of USB Link Controllers (link to Web Brochure) and USB Physical layers (link to web brochure) that are silicon proven and USB-IF certified. See CI12343tn, the first industry’s USB High Speed PHY with Certification in TSMC65nm.

USB-HS Core Blocks Diagram
USB-HS Core Blocks Diagram
USB2.0 PHY Functional Diagram
USB2.0 PHY Functional Diagram

For more details visit www.chipidea.com or contact us at sales@mips.com.

Best Regards
The Chipidea Team - Your Silicon IP Partner