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| Print this page | Download the PDF File | Close Window | FLASH NEWS #4-2005 |
| CHIPIDEA announces Silicon validation of a very compact 90nm 10-bit /105MHz ADC |
CHIPIDEA, listed by Gartner Inc. as the
world leading Analog and Mixed-Signal IP player, announces silicon
validation of the CI3514hm,
a very compact 90nm 10-bit/105MHz ADC, with very low power dissipation
and power-down modes for standby operation. This new state-of-the-art
IP Core enhances Chipidea´s IP portfolio in 90nm CMOS processes
and continues the accelerated silicon validation program started in
2004.
 Silicon Achievements  ApplicationFor SoC integration, Chipidea offers a wide range of Analog-Digital Interface Systems for Audio, Video, Multimedia, Data-Communications and Connectivity, including Power and Clock Management functions. |
Brief Description The ADC architecture employs 9 multi-bit pipelined stages to achieve sampling rates above 105 MS/s with low power dissipation. Digital error correction is employed to reduce DNL errors. A dedicated S/H circuit is built-in to provide low jitter noise. The references voltages are internally generated from an external bandgap and are provided outside for decoupling purposes. It includes an adjustable bias current generation to minimize power dissipation at lower conversion rates. A power down capability is included for extremely low power dissipation in stand-by mode.
Block Diagram |